K 10
svn:author
V 5
peter
K 8
svn:date
V 27
2003-12-11T04:47:53.000000Z
K 7
svn:log
V 177
CACHE_LINE_SIZE is 64 on athlon and amd64 chips, not 32.  This should
probably be 128 since that is what the hardware prefetch fill size is
on both the p3, p4 and athlon* cpus.

END