K 10
svn:author
V 6
marius
K 8
svn:date
V 27
2005-04-16T15:05:56.000000Z
K 7
svn:log
V 633
- MFi386: sys/i386/i386/intr_machdep.c rev. 1.11
  Don't use atomic ops to increment interrupt stats.
  On sparc64 this reduces delay until tick interrupts are service by 1/10th
  on average. In turn this reduces the clock drift caused by these delays
  so there's less drift which has to be compensated in tick_hardclock().
  This includes switching from atomically incrementing the global cnt.v_intr
  to the asm equivalent of PCPU_LAZY_INC(cnt.v_intr) in exception.S
- Correct some comments to match the registers actually used.
- Correct some format specifiers, interrupt levels passed in are u_int.
- Use FBSDID.

Ok'ed by:	jhb

END