K 10
svn:author
V 6
mjacob
K 8
svn:date
V 27
2006-02-26T07:44:31.000000Z
K 7
svn:log
V 258
a) Delay for port enable to succeed should be 30 seconds (at least) for
*both* SAS and FC, not just SAS.

b) Don't tell the chip we want it to do FIFO signalling if we actually
don't set up the address where the FIFO signal is supposed to be written
(oops).

END