K 10
svn:author
V 6
cognet
K 8
svn:date
V 27
2006-05-31T15:50:33.000000Z
K 7
svn:log
V 289
If our buffer is not aligned on the cache line size, write back/invalidate
the first and last cache line in PREREAD, and just invalidate the cache
lines in POSTREAD, instead of write-back/invalidating in POSTREAD, which
could lead to stale data overriding what has been transfered by DMA.

END