K 10
svn:author
V 3
raj
K 8
svn:date
V 27
2008-10-16T19:06:24.588152Z
K 7
svn:log
V 175
Eliminate flushing of L2 cache in ARM context switch routines.

With VIPT L2 cache such syncing not only is redundant, but also a performance
penalty.

Pointed out by:	cognet

END