K 10
svn:author
V 6
marius
K 8
svn:date
V 27
2008-12-07T23:02:37.799763Z
K 7
svn:log
V 357
- According to the corresponding Linux, NetBSD and OpenSolaris
  drivers, there should be a 1us delay after every write when
  bit-banging the MII. Also insert barriers in order to ensure
  the intended ordering. These changes hopefully will solve the
  bus wedging occasionally experienced with DM9102A since r182461.
- Deobfuscate dc_mii_readreg() a bit.

END