K 10
svn:author
V 10
nwhitehorn
K 8
svn:date
V 27
2009-04-12T03:03:55.159609Z
K 7
svn:log
V 231
Rework the way we get the cacheline size. Instead of having a table of
CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz
instruction to measure it. Also make dcbz behave the way you would
expect on PPC 970.

END