K 10
svn:author
V 3
jhb
K 8
svn:date
V 27
2009-05-18T19:33:59.422376Z
K 7
svn:log
V 144
Bump CACHE_LINE_SIZE to 128 for x86.  Intel's manuals explicitly recommend
using 128 byte alignment for locks.  (See IA-32 SDM Vol 3A 7.11.6.7)

END