K 10
svn:author
V 3
imp
K 8
svn:date
V 27
2009-08-15T19:48:14.603787Z
K 7
svn:log
V 308
The UART device infrasturcture wants these defined.  Define them just
like we do in Malta.  We may want to look at consolidating things
because *ALL* mips will *ALWAYS* be memory mapped.  The only wrinkle
is that the tag may need to be a custom one (see endian issues with
the Atheros port for one example).

END