K 10
svn:author
V 4
neel
K 8
svn:date
V 27
2009-10-20T04:36:08.811689Z
K 7
svn:log
V 175
Fix a bug where we would think that the L1 instruction and data cache are
present even though the line size field in the CP0 Config1 register is 0.

Approved by: imp (mentor)

END