K 10
svn:author
V 3
rrs
K 8
svn:date
V 27
2009-11-06T12:52:51.737536Z
K 7
svn:log
V 332
Ok With this commit we actually get through
the mi_startup (or to the last of it).. and
hit a panic after :

uart0: <16550 or compatible> on iodi0
Trap cause = 2 (TLB miss....)

I did have to take the pci bus OUT of the
build to get this far, hit a cache error with
the PCI code in. Interesting thing is the machine
reboots too ;-)

END