K 10
svn:author
V 3
mav
K 8
svn:date
V 27
2009-11-26T14:56:58.936801Z
K 7
svn:log
V 362
MFC r199645, r199646:
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.

END