K 10
svn:author
V 3
mav
K 8
svn:date
V 27
2010-01-10T16:05:05.717019Z
K 7
svn:log
V 245
While AHCI specification tells that multi-vector MSI doesn't use global IS
register, nVidia chipsets have different oppinion, requiring every interrupt
to be acknowledged there.

While there, add interrupt descriptions in multi-vector MSI mode.

END