K 10
svn:author
V 4
neel
K 8
svn:date
V 27
2010-03-04T05:23:08.662287Z
K 7
svn:log
V 393
Add support for CPUs with cache coherent DMA. The two main changes are:

- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
  requests on these CPUs.

- The bus_dmamap_sync() is a no-op for these CPUs.

A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.

Reviewed by: gonzo, imp

END