K 10
svn:author
V 6
marius
K 8
svn:date
V 27
2010-03-17T20:23:14.890436Z
K 7
svn:log
V 461
- Add TTE and context register bits for the additional page sizes supported
  by UltraSparc-IV and -IV+ as well as SPARC64 V, VI, VII and VIIIfx CPUs.
- Replace TLB_PCXR_PGSZ_MASK and TLB_SCXR_PGSZ_MASK with TLB_CXR_PGSZ_MASK
  which just is the complement of TLB_CXR_CTX_MASK instead of trying to
  assemble it from the page size bits which vary across CPUs.
- Add macros for the remainder of the SFSR bits, which are useful for at
  least debugging purposes.

END