K 10
svn:author
V 3
alc
K 8
svn:date
V 27
2010-03-21T00:13:11.449191Z
K 7
svn:log
V 223
I am told by AMD that the machine check hardware on the instruction TLB
won't generate bogus exceptions.  Therefore, the implementation of the
"unofficial" workaround needn't mask L1TP errors by the instruction cache
unit.

END