K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2011-03-20T09:08:45.904639Z
K 7
svn:log
V 535
Cave in and disable the ADC DC gain/offset calibrations if they're
not needed.

These calibrations are only applicable if the chip operating mode
engages both interleaved RX ADCs (ie, it's compensating for the
differences in DC gain and DC offset -between- the two ADCs.)
Otherwise the chip reads values of 0x0 for the secondary ADC
(as I guess it's not enabled here) and thus writes potentially
bogus info into the chip.

I've tested this on the AR9160 and AR9280; both behave themselves
in 11g mode with these calibrations disabled.

END