K 10
svn:author
V 7
yongari
K 8
svn:date
V 27
2011-05-12T17:11:31.529892Z
K 7
svn:log
V 343
Explicitly clear 1000baseT control register for F1 PHY used in
AR8132 FastEthernet controller. The PHY has no ability to
establish a gigabit link. Previously only link parters which
support down-shifting was able to establish link.
This change should fix a long standing link establishment issue of
AR8132.

PR:		kern/156935
MFC after:	1 week

END