K 10 svn:author V 6 adrian K 8 svn:date V 27 2011-07-16T00:30:23.543668Z K 7 svn:log V 335 The i8259 controller is initialized incorrectly on MALTA. It writes mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan END