K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2011-09-14T07:56:25.178243Z
K 7
svn:log
V 1443
Add support to use the non read-and-copy interrupt register path.

There appears to be a subtle race condition in the AR_ISR_RAC
path where some of the secondary conditions would be not show
up. This unfortunately includes TX events such as EOL.

The reference driver includes an alternate path which instead
uses the AR_ISR and AR_ISR_S{0,1,2,3,4,5} registers instead of
AR_ISR_RAC and the shadow AR_ISR_S{0,1,2,3,4,5}_S registers.

Here, the interrupts being handled are written back to the
status register, clearing them.

For interrupts caused by secondary registers, clear those bits
instead of the relevant bit in AR_ISR. That way if an event
occurs between the ISR_ISR_Sx read and write (clear), it won't
be cleared; and it'll trigger another interrupt.

This won't _entirely_ limit the TX hangs because of the
existing txqactive() race going on between the interrupt
handler and the TX process. I'll address that in a future commit.

Note: I should also do this for the AR5212 series NICs as well
as some of them may suffer from the same race.

Finally - for now, never set the relevant HAL capability that
I've introduced; I'll set it when I know which chips work and
which don't.

Finally finally - ath9k doesn't do this for the pre-ar9003
NICs but does for AR9300 v2.0 and later. ie, the AR9300 NIC
interrupt code has this RAC capability check, and only enables
it for AR9300 v2.0 MAC versions.

Obtained from:	Atheros, Linux ath9k

END