K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2011-09-28T15:36:08.770655Z
K 7
svn:log
V 526
Flip back to the atheros defaults for now. Now that I've figured out why I'm
getting performance issues on these mips boards (interrupts occuring in a race
window between critical_enter and "wait", and thus being delayed until the
next interrupt), this provides better RX performance under heavy UDP load.

This doesn't fix the issue - it just means that under heavy UDP load, I'm
not getting 1 RX interrupt every 2ms. This turns out not to be often enough
in some occasional situations. Some more research is needed though..

END