K 10
svn:author
V 8
jchandra
K 8
svn:date
V 27
2011-11-21T16:43:24.719824Z
K 7
svn:log
V 294
Do dcache flush on CPU core before enabling threads.

The dcache flush has to be done using the core control registers before
splitting the L1D cache by enabling the hardware threads.

Also replace .word calls for mfcr/mtcr with a C macro.

In collaboration with: prabhath at netlogicmicro com

END