K 10
svn:author
V 3
alc
K 8
svn:date
V 27
2011-12-04T18:55:19.389434Z
K 7
svn:log
V 618
MFC r219157
  Make a change to the implementation of the direct map to improve
  performance on processors that support 1 GB pages.  Specifically, if the
  end of physical memory is not aligned to a 1 GB page boundary, then map
  the residual physical memory with multiple 2 MB page mappings rather than
  a single 1 GB page mapping.  When a 1 GB page mapping is used for this
  residual memory, access to the memory is slower than when multiple 2 MB
  page mappings are used.  (I suspect that the reason for this slowdown is
  that the TLB is actually being loaded with 4 KB page mappings for the
  residual memory.)

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