K 10
svn:author
V 7
yongari
K 8
svn:date
V 27
2012-01-06T19:26:31.183435Z
K 7
svn:log
V 3539
MFC r228326-228327,228331-228332:
r228326:
  Controller does not require TX start command for every frame.  So
  send a single TX command after setting up all TX frames.  This
  removes unnecessary register accesses and bus_dmamap_sync(9) calls.
  et(4) uses TX interrupt moderation so it's possible to have TX
  buffers that were already transmitted but waiting for TX completion
  interrupt.  If the number of available TX descriptor is less then
  1/3 of total TX descriptor, try reclaiming first to get enough free
  TX descriptors before setting up TX descriptors.
  After r228325, et_txeof() no longer tries to send frames after
  reclaiming TX buffers.  That change was made to give more chance
  to transmit frames in main interrupt handler since we can still
  send frames in interrupt handler with RX interrupt.  So right
  before exiting interrupt hander, after enabling interrupt, try to
  send more frames.  This gives slightly better performance numbers.

  While I'm here reduce number of spare TX descriptors from 8 to 4.
  Controller does not require reserved TX descriptors, it was just to
  reduce TX overhead.  After r228325, driver has much lower TX
  overhead so it does not make sense to reserve 8 TX descriptors.

r228327:
  Remove et_enable_intrs(), et_disable_intrs() functions and
  manipulation of interrupt register access is done through
  CSR_WRITE_4 macro.  Also add disabling interrupt into et_reset()
  because we want interrupt disabled state after controller reset.
  While I'm here slightly change interrupt handler to be more
  readable one.

r228331:
  Rework link state tracking and TX/RX MAC configuration.
   o Do not report link status if driver is not running.
   o TX/RX MAC configuration should be done with resolved speed,
     duplex and flow control after establishing a link so it can't
     be done in driver initialization routine.
     Move the configuration to miibus_statchg callback which will be
     called whenever any link state change is detected.
     At this moment, flow-control is not enabled yet mainly because
     I was not able to set correct flow control parameters to
     generate TX pause frames.
   o Now TX/RX MAC is enabled only when a valid link is detected.
     Rearragnge hardware initialization routine a bit to leave
     enabling MAC to miibus_statchg callback.  In order to that,
     TX/RX DMA engine is enabled in et_init_locked().
   o Introduce ET_FLAG_LINK flag to track current link state.
   o Introduce ET_FLAG_FASTETHER flag to mark whether controller is
     fast ethernet.  This flag is checked in miibus_statchg callback
     to know whether PHY established a valid link.
   o In et_stop(), TX/RX MAC is explicitly disabled instead of
     relying on et_reset().  And move et_reset() from et_stop() to
     controller initialization.  Controler reset is not required here
     and it would also clear critial registers(i.e station address,
     RX filter configuration, WOL etc) that are required to make WOL
     work.
   o Switching to current media is done in et_init_locked() after
     setting IFF_DRV_RUNNING flag.  This should ensure reliable
     auto-negotiation/manual link establishment.
   o In et_start_locked(), check whether driver got a valid link
     before trying to send frames.
   o Remove checking a link in et_tick() as this is done by
     miibus_statchg callback.

r228332:
  Implement hardware MAC statistics counter.  Counters could be
  queried with dev.et.%d.stats sysctl node where %d is an instance of
  device.

END