K 10
svn:author
V 7
rwatson
K 8
svn:date
V 27
2012-08-25T08:31:21.085931Z
K 7
svn:log
V 323
Add preliminary support for the SRI International / University of Cambridge
Bluespec Extensible RISC Implementation (BERI) processor.  BERI is a 64-bit
MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs,
and is being used for CPU and OS research at several institutions.

Sponsored by:   DARPA, AFRL

END