K 10
svn:author
V 3
jhb
K 8
svn:date
V 27
2012-10-09T18:45:08.496034Z
K 7
svn:log
V 1108
MFC 201279,201280,201286,213907,214146,220195,222753,223371,225515,235833:
Various fixes to managing PCI BARs including proper support for managing
PCI ROM BARs:
- Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove
  special handling for the PCIR_BIOS decoding enable bit from the cardbus
  driver.  The PCIR_BIOS BAR does include type bits like other BARs.
  Instead, it is always a 32-bit non-prefetchable memory BAR where the low
  bit is used as a flag to enable decoding.
- Explicitly track the state of all known BARs for each PCI device.  The PCI
  bus driver will now remember the size of a BAR obtained during the initial
  bus scan and use that size when doing lazy resource allocation rather than
  resizing the BAR.  The bus driver will now also report unallocated BARs to
  userland for display by 'pciconf -lb'.
- Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and
  properly handle ROM BIOS BARs in PCI-PCI bridges.  The PCI bus now also
  properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge.

Tested by:	John Kozubik  john kozubik com

END