K 10
svn:author
V 7
yongari
K 8
svn:date
V 27
2012-11-26T02:41:30.631141Z
K 7
svn:log
V 1655
MFC r241388-241393:
r241388:
  If the maximum payload size is 256 bytes or more, set the DMA write
  water mark to 256 bytes.  Otherwise controller will encounter DMA
  write under run errors and would result in RX DMA hang. If the
  maximum payload size is 128 bytes, the water mark is set to 128
  bytes as usual.
  While here, set maximum read request size to 2048 for BCM5719/BCM5720.
  For other PCIe devices, use 4096. And reprogram the maximum read
  request size whenever device reset is performed.

r241389:
 On PHY write error use hex number to show the value.
 Add more comments.

r241390:
  Honor PHY type fiber for BCM5717/BCM5718/BCM5719/BCM5720.

r241391:
  Do not force PCIe 1.0a mode in device reset on BCM5717 and newer
  controllers. BCM5785 does not require PCI 1.0a mode as well during
  reset.

r241392:
  Fix a long standing VCPU reset sequence bug on BCM5906.
  The VCPU(Virtual CPU) of BCM5906 is used to provide a mechanism to
  control the bootcode execution and to pick up configuration data
  stored inside the EEPROM.
  The bootcode of BCM5906 will check the BGE_VCPU_STATUS_DRV_RESET
  bit to decide which booting procedure to choose.
  Data sheet indicates the VCPU of BCM5906 should set
  BGE_VCPU_STATUS_DRV_RESET bit *before* VCPU reset or global reset.

r241393:
  Remove unnecessary delay. I don't see any comments in data sheet
  that requires 10ms delay after device reset.  Because that code was
  there from day 1, I guess it was added to give enough settlement
  time after updating BGE_MAC_MODE register.
  The recommended delay time for BGE_MAC_MODE after updating is 40us
  and it was already done in r241219.

END