K 10
svn:author
V 9
jimharris
K 8
svn:date
V 27
2012-12-18T23:27:18.081020Z
K 7
svn:log
V 167
Map BAR 4/5, because NVMe spec says devices may place the MSI-X table
behind BAR 4/5, rather than in BAR 0/1 with the control/doorbell registers.

Sponsored by:	Intel

END