K 10
svn:author
V 6
marcel
K 8
svn:date
V 27
2013-01-07T03:47:59.042336Z
K 7
svn:log
V 2033
o   Add a work-around for the race condition between PIO read and DMA.
    This is implemented by using a new busdma_iommu_sync method that
    busses can implement. The method is implemented by the SGI PCI HC
    driver to make sure the DMA has completely landed in memory by
    triggering an interrupt and waiting for it to arrive in the
    designated memory location. Any outstanding DMA transactions will
    have completed if that happens. The work-around is derived from
    Linux.
    The upshot of using a new method is that either nexus or root_bus
    can implement the CPU cache flushing and/or invalidation and in a
    way suitable for the platform. Thus: the method provides the MI
    abstraction we need.
o   Change the existing busdma_iommu_* methods to take the bus device
    as the first argument. These methods can now access bus softc
    structures and other "local" information in order to implement
    xlate, map and unmap. This also applies to the new sync method.
o   Add a flags field to the mtag structure to hold platform flags.
    Platform flags are a way for different devices to communicate
    with each other, as well as provide a means for drivers to handle
    very platform specific hacks/kluges. The platform-specific flags
    are saved in the memory descriptor so that they can be used to
    communicate between different methods as well.
    Introduce a new platform flag called BUSDMA_MD_IA64_DIRECT32. The
    flag is used by the SGI SHub and PCI drivers to implement 32-bit
    direct-mapped DMA. The flag is set in the PCI's xlate method and
    used by the SHub's xlate and map method, as well as the PCI's
    map method.
o   Reimplement busdma_sync() as a wrapper around busdma_sync_range()
    with address 0 and size ~0.
o   In _busdma_iommu_xlate() always align and round to the cache line
    size. Since we're allocating DMA memory, we can and should avoid
    complications or performance reductions that come from having to
    maintain coherence -- either in S/W or H/W.

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