K 10
svn:author
V 4
neel
K 8
svn:date
V 27
2013-06-29T23:07:41.098250Z
K 7
svn:log
V 465
Rework the TLB invalidation functions to support Intel's extended page tables.

The basic idea is that we keep track of the generation number of the EPT in
the 'struct pmap'. The vcpu context keeps a cached copy of this generation
number and invalidates its EPT mappings on a mismatch.

If any vcpus are executing at the time of the invalidation then we use an
IPI_AST to force them to trap into the hypervisor. They will do an "invept"
on the subsequent vmresume.

END