K 10
svn:author
V 3
mav
K 8
svn:date
V 27
2013-11-10T23:48:16.938191Z
K 7
svn:log
V 219
Use relaxed (write-only) memory barriers when writing some of queue index
registers (for now on ISP2400+).  We never read those registers back and
AFAIK their semantics does not require any immediate reaction on write.

END