K 10 svn:author V 3 ian K 8 svn:date V 27 2014-02-23T22:52:48.332424Z K 7 svn:log V 332 If the L2 cache type is PIPT, pass a physical address for a flush. While this is technically more correct, I don't think it much matters, because the only thing in the tree that calls cpu_flush_dcache() is md(4) and I'm > 99% sure it's bogus that it does so; md has no ability to do anything that can perturb data cache coherency. END