K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2014-03-16T08:39:46.006752Z
K 7
svn:log
V 222
The AR71xx has APB interrupts in the MISC registers from 0-7, later
chips have more.

So for now, let's allow more.  We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.

END