K 10
svn:author
V 3
ian
K 8
svn:date
V 27
2014-04-27T20:16:51.078345Z
K 7
svn:log
V 408
Flush and invalidate caches on each CPU as part of handling IPI_STOP.

Flushing the caches is required before doing a panic dump, but ARM
doesn't provide a flavor of flush that gets broadcast to other cores.
However, all cores except one are stopped before doing a dump, so this
works around the lack of a global flush/invalidate by doing it locally
on each CPU as part of stopping.

Discussed with:	cognet@

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