K 10
svn:author
V 3
ian
K 8
svn:date
V 27
2014-05-24T16:21:16.592607Z
K 7
svn:log
V 671
Eliminate one of the causes of spurious interrupts on armv6.  The arm weak
memory ordering model allows writes to different devices to complete out
of order, leading to a situation where the write that clears an interrupt
source at a device can complete after a write that unmasks and EOIs the
interrupt at the interrupt controller, leading to a spurious re-interrupt.

This adds a generic barrier function specific to the needs of interrupt
controllers, and calls that function from the GIC and TI AINTC controllers.
There may still be other soc-specific controllers that need to make the call.

Reviewed by:	cognet, Svatopluk Kraus <onwahe@gmail.com>
MFC after:	3 days

END