K 10
svn:author
V 3
mav
K 8
svn:date
V 27
2014-09-14T22:13:19.030811Z
K 7
svn:log
V 387
Add couple memory barries to serialize tdq_cpu_idle and tdq_load accesses.

This change fixes transient performance drops in some of my benchmarks,
vanishing as soon as I am trying to collect any stats from the scheduler.
It looks like reordered access to those variables sometimes caused loss of
IPI_PREEMPT, that delayed thread execution until some later interrupt.

MFC after:	3 days

END