K 10
svn:author
V 3
mav
K 8
svn:date
V 27
2014-09-17T14:06:21.180808Z
K 7
svn:log
V 413
MFC r271604, r271616:
Add couple memory barriers to order tdq_cpu_idle and tdq_load accesses.

This change fixes transient performance drops in some of my benchmarks,
vanishing as soon as I am trying to collect any stats from the scheduler.
It looks like reordered access to those variables sometimes caused loss of
IPI_PREEMPT, that delayed thread execution until some later interrupt.

Approved by:	re (marius)

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