K 10
svn:author
V 4
neel
K 8
svn:date
V 27
2014-10-17T03:04:38.764354Z
K 7
svn:log
V 284
Hide extended PerfCtr MSRs on AMD processors by clearing bits 23, 24 and 28 in
CPUID.80000001H:ECX.

Handle accesses to PerfCtrX and PerfEvtSelX MSRs by ignoring writes and
returning 0 on reads.

This further reduces the number of unimplemented MSRs hit by a Linux guest
during boot.

END