K 10
svn:author
V 4
neel
K 8
svn:date
V 27
2014-12-16T06:33:57.976310Z
K 7
svn:log
V 307
For level triggered interrupts clear the PIC IRR bit when the interrupt pin
is deasserted. Prior to this change each assertion on a level triggered irq
pin resulted in two interrupts being delivered to the CPU.

Differential Revision:	https://reviews.freebsd.org/D1310
Reviewed by:	tychon
MFC after:	1 week

END