K 10
svn:author
V 3
kib
K 8
svn:date
V 27
2015-02-27T11:13:46.132152Z
K 7
svn:log
V 366
Since all generations of Intel CPUs have errata which causes hang on
the cache line flush in the LAPIC page, keep direct map page covering
LAPIC mapped uncached.

To have the (incomplete) check for the LAPIC range in
pmap_invalidate_cache_range() working, lapic_paddr must be initialized
in x2APIC mode too.

Sponsored by:	The FreeBSD Foundation
MFC after:	2 months

END