K 10
svn:author
V 5
gonzo
K 8
svn:date
V 27
2015-03-05T21:41:58.892575Z
K 7
svn:log
V 600
Add sysctls to control PS-PL level shifters and FCLK settings.

PL (programmable logic) uses FCLK0..FCLK3 as a clock sources.
Normally they're configured by first stage boot loader (FSBL)
and normal user never has to touch them. These sysctls may come
useful for hardware developers

hw.fpga.fclk.N.source: clock source (IO, DDR, ARM)
hw.fpga.fclk.N.freq: requested frequency in Hz
hw.fpga.fclk.N.actual_freq: actual frequency in Hz (R/O)

hw.fgpa.level_shifters: 0/1 to enable/disable PS-PL level shifters,
    normally they're enabled either by FSBL or after programming
    FPGA through devcfg(4)

END