K 10
svn:author
V 3
jhb
K 8
svn:date
V 27
2015-04-02T01:02:42.791615Z
K 7
svn:log
V 341
MFC 276724:
On some Intel CPUs with a P-state but not C-state invariant TSC the TSC
may also halt in C2 and not just C3 (it seems that in some cases the BIOS
advertises its C3 state as a C2 state in _CST).  Just play it safe and
disable both C2 and C3 states if a user forces the use of the TSC as the
timecounter on such CPUs.

PR:		192316

END