K 10
svn:author
V 6
sbruno
K 8
svn:date
V 27
2015-06-01T18:15:50.289388Z
K 7
svn:log
V 789
Handle Intel Errata notice 12.  Reading the ICR can lead to a case where
the driver would process a link status or other status and ignore a
simultaneous interrupt for an incoming packet.  In the msi link handler
assume that we should schedule tx/rx processing by setting the ICS to
generate a soft interrupt for tx/rx processing to ensure that this race
doesn't cause missed packets.

Handle Intel Errata notice 3.  Always set TARC bit 26.

Handle Intel Errata regarding multiqueue behavavior.  Always set TARC
bits to enable compensation mode of 1/1 for the 2 queues.  Always set
TARC bits 23, 24 & 25 in multiqueue operation.

Add new DB command for debugging to fully reset the adapter when testing.

Thanks to Intel for their continuing support of FreeBSD.

Submitted by:	jfv and erj

END