K 10
svn:author
V 3
zbb
K 8
svn:date
V 27
2015-07-17T14:33:47.211710Z
K 7
svn:log
V 670
Fix possible coherency issues between PEs related to I-cache

Basing on B.2.3.4:
Synchronization and coherency issues between data and
instruction accesses.

To ensure that modified instructions are visible to all PEs
(Processing Elements) in a shareability domain one need to
perform following sequence:
    1. Clean D-cache
    2. Ensure the visibility of data cleaned from cache
    3. Invalidate I-cache
    4. Ensure completion
    5. In SMP system PE must issue isb to ensure execution of the
       modified instructions

Reviewed by:   andrew
Obtained from: Semihalf
Sponsored by:  The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D3106

END