K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2015-10-30T23:07:32.744119Z
K 7
svn:log
V 566
arge: do an explicit flush between updating the TX ring and starting transmit.

The MIPS busdma sync operations currently are a big no-op on coherent memory.
This isn't strictly correct behaviour as we need a SYNC in here to ensure that
the writes have finished and are visible in main memory before the MMIO accesses
occur.  This will have to be addressed in a later commit.

But, before that happens, let's at least do a flush here to make things
more "correct".

This is required for even remotely sensible behaviour on mips74k with
write-through memory enabled.

END