K 10
svn:author
V 4
mmel
K 8
svn:date
V 27
2015-11-30T17:09:25.567943Z
K 7
svn:log
V 409
ARM: create new memory attribute for writethrough cacheable memory.
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
  VM_MEMATTR_WRITE_BACK, it's used in DRM code

Note:
 Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
 WT requests is treated as uncacheable.

Approved by:	kib (mentor)

END