K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2015-12-21T01:48:16.015659Z
K 7
svn:log
V 583
[mips] print out l2 cache configuration if it exists.

The Ingenic JZ7480 SoC that is on the Imagination Technologies CI20 board
has an L2 cache:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 8
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: Ingenic Xburst processor v79.2
  MMU: Standard TLB, 32 entries
  L1 i-cache: 8 ways of 128 sets, 32 bytes per line
  L1 d-cache: 8 ways of 128 sets, 32 bytes per line
  L2 cache: 8 ways of 256 sets, 128 bytes per line, 256 KiB total size
  Config1=0xbe67338b<WatchRegs,EJTAG,FPU>
  Config2=0x80000267
  Config3=0x20

END