K 10
svn:author
V 6
adrian
K 8
svn:date
V 27
2015-12-24T04:37:19.793122Z
K 7
svn:log
V 517
Add missing \n.

Otherwise you end up with:

Cache info:
  picache_stride    = 4096
  picache_loopcount = 16
  pdcache_stride    = 4096
  pdcache_loopcount = 8
cpu0: MIPS Technologies processor v80.150
  MMU: Standard TLB, 32 entries (4K 16K 64K 256K 1M 16M 64M 256M pg sizes)
  L1 i-cache: 4 ways of 512 sets, 32 bytes per line
  L1 d-cache: 4 ways of 256 sets, 32 bytes per line
  L2 cache: disabled  Config1=0xbee3519e<PerfCount,WatchRegs,MIPS16,EJTAG>
  Config2=0x80000000
  Config3=0x2420

Tested:

* MT7620 SoC

END