K 10
svn:author
V 2
br
K 8
svn:date
V 27
2016-04-22T15:12:05.121439Z
K 7
svn:log
V 208
Add memory barriers (fence instructions) so the data wrotten by hardware
to physical address now can be read by VA.

This fixes operation on Rocket Core (FPGA).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5

END