K 10
svn:author
V 2
br
K 8
svn:date
V 27
2016-09-01T14:58:11.213648Z
K 7
svn:log
V 374
o Separate rtc and timecmp registers: they are different across
  RISC-V cpu implementations.
o Update RocketChip device tree source (DTS).

We now support latest verison of RocketChip synthesized on
Xilinx FPGA (Zedboard).

RocketChip is an implementation of RISC-V processor written on
Chisel hardware construction language.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5

END